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LATTICE LAUNCHES INDUSTRY'S LOWEST POWER, HIGHEST VALUE FPGA DEVICES
–SERDES-Capable LatticeECP3 Family Consumes Half the Power and is Half the Price of Competitive Devices– ;

	FEBRUARY 23, 2009
	HILLSBORO, OR - FEBRUARY 23, 2009 - Lattice Semiconductor Corporation (NASDAQ: LSCC) today announced its third generation high value FPGAs, the mid-range 65nm LatticeECP3™ family, which offers the industry's lowest power consumption and price of any SERDES-capable FPGA device. The LatticeECP3 FPGA family offers multi-protocol 3.2G SERDES with XAUI jitter compliance, DDR3 memory interfaces, powerful DSP capabilities, high density on-chip memory and up to 149K LUTS, all with half the power consumption and half the price of competitive SERDES-capable FPGAs. The entire LatticeECP3 family is manufactured using Fujitsu's advanced low power process technology, and is the only 65nm mid-range, high value FPGA family in the industry. "Like our award winning LatticeECP2M™ devices before it, our LatticeECP3 family once again redefines mid-range, value-based FPGAs, not only by further reducing costs, but also by reducing static power consumption by 80% and total power consumption by over 50% for typical designs, compared to competitive SERDES-capable FPGAs. By making careful design choices and minimizing die size, we are able to offer designers the benefits of high speed serial I/O and processing capabilities, without the power and cost premiums typically associated with these types of devices," said Sean Riley, Corporate Vice President and General Manager of High Density Solutions.
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	Thursday, September 09, 2010